Methods of phase controlling of a data signal using a counter clock approach as well as corresponding counter clock circuits are in generally known in the state of the art. They are used, for example for distributing digital data signals among different, spatially separated modules, units or parts of a circuit arrangement or of different circuits. The data signal has to be sampled with the data clock for evaluating the data signal. Thereby, the data clock could be recovered from the data signal itself or a generated clock could be used in case of a known data clock. In order to provide the different modules, units or parts of a circuit arrangement with the same clock, the clock is usually transmitted between the modules, units or parts of a circuit arrangement.
In general a data signal is transmitted from a first unit or part, which can in generally considered as a data source, to a second unit or part, which can correspondingly considered as a data sink. Using a counter clock approach, in particular the clock is transmitted in a counter propagating direction regarding the propagation of the data signal. Thereby, a clock, which is also called a main clock or master clock, is generated inside or fed to the data sink and from there it is transmitted to the data source as the counter propagating clock.
A counter clock circuit arrangement of the state of the art comprises a first latch at the data source unit and a second latch at the data sink unit. The data sink generates or receives a main clock. At the data sink, the main clock is split into a data sink clock and a counter propagated clock, which is transmitted to the data source. The processing in the data source is controlled with the counter propagated clock. In more detail, the data signal is synchronised with the counter propagated clock at the data source and with the data sink clock or main clock, respectively, at the data sink using the first and second latch. Due the periodic character of the clock several discrete values are allowed. However, variations of the data/clock link between data source and data sink and/or circuit propagation delays exceeding the clock phase margin of the data sink latch will cause bit errors. In particular, at high clock rates it is difficult to stabilise the timing.
Throughout this specification including in the claims, the expression “data sink clock” denotes a clock, which is fed to the data sink or generated in the data sink and is provided for controlling the timing of certain functions at the data sink, such as duration of signal elements or a sampling rate or for synchronisation of a transmission facility.
Throughout this specification including the claims, the expression “counter propagating clock” or “counter clock” denotes a clock, which is provided for controlling the timing of certain function at the data source, such as duration of signal elements or a sampling rote or for synchronisation of a transmission facility, and is transmitted from the data sink.
Another approach in the prior art is a counter clock circuit with a First-In-First-Out (FIFO) memory. In comparison with the above mentioned circuit of the prior art a FIFO memory is provided at the data sink and a co-propagating clock is transmitted from the data source to the data sink. The co-propagating clock is realised as the counter clock, which is back-coupled from the data source to the data sink. The data are written in the FIFO under control of the co-propagating clock, which is phase matched with the data of the data source and has an arbitrary phase with respect to the main clock. The data are red out of the FIFO using the data sink clock or main clock, respectively, thereby ensuring a proper clock data phase at the input register of the data sink. Phase fluctuations or transmitting differences of the signals are compensated by temporarily writing in more data than reading out or reading out more date than writing in. Thus, the FIFO memory is used to compensate temporary propagation variations of the data/clock link between data source and data sink and/or circuit propagation delays.
However, the depth of the FIFO memory limits the correction abilities of the circuit. Small fluctuations or short-term variations could be tackled in this way. In contrary, a constant or a long-term potential phase drift of the circuit even by small deviations would, sooner or later, certainly leads to an exceeding of the memory limits and thus to bit errors.